Since the development of integrated circuit technology, computers and computer storage devices have been made from wafers of semiconductor material comprising a plurality of integrated circuits. After a wafer is made, the circuits are typically separated from each other by dicing the wafer into small chips. Thereafter, the chips are bonded to carriers of various types, interconnected by wires and packaged. Along with being time consuming, costly and unreliable, the process of physically attaching wires to interconnect chips often produces undesirable signal delays, especially as the frequency of device operation increases.
As an improvement over this traditional technology, stacks or packages of multiple semiconductor chips have become popular, e.g., reference U.S. Pat. No. 4,525,921, entitled "High-Density Electronic Processing Package--Structure and Fabrication;" U.S. Pat. No. 4,706,166, entitled "High-Density Electronic Modules--Process and Product;" U.S. Pat. No. 4,983,533, entitled "High-Density Electronic Modules--Process & Product;" U.S. Pat. No. 5,104,820, entitled "Method of Fabricating Electronic Circuitry Unit Containing Stacked IC Layers Having Lead Rerouting;" and U.S. Pat. No. 5,270,261, entitled "Three-Dimensional Multichip Package Methods of Fabrication."
A typical multichip electronic module consists of multiple integrated circuit chips adhesively secured together as a monolithic structure. A metallization pattern is often provided on one (or more) side surface(s) of the module for chip interconnections and for electrical connection to circuitry external to the module. The metallization pattern can include both individual contacts and bussed contacts. Typically, the multichip module is positioned on a surface of a substrate, which may also have its own metallization pattern.
High production fabrication of monolithic modules is complicated by the presence of the surface metallization(s). Further, fabrication techniques for monolithic modules typically require the use of a ceramic end cap on the module to transform interconnection wiring on an exposed surface of an end semiconductor chip to a side surface metallization interconnecting semiconductor chips in the module. The processes and structures disclosed herein address these and other complications/disadvantages of the existing high density electronic packaging art.